The present invention relates to electronic data buffers, and more particularly to asynchronous data buffers having a self-diagnostic capability for detecting a hardware fault.
Electronic data buffers are utilized in many applications. In the field of telecommunications, asynchronous buffers are used, for example, to transfer digital data between two systems having different reference clocks. That is, a stream of data is clocked into the buffer under the control of a first system's reference clock (henceforth referred to as a "write clock" (WCLK)), and is stored until it is read out of the buffer in response to assertion of the second system's reference clock (henceforth referred to as a "read clock" (RCLK)), which operates asynchronously with respect to the WCLK. The buffer will typically include hardware to ensure that data is clocked out in the same order in which it was clocked in.
A conventional asynchronous buffer 100 is illustrated in FIG. 1. The buffer includes a decoder 101, having N (preferably =2.sup.m) outputs, only one of which is active at a time. An m-bit wide write address (WADR) signal 119 that is provided by a write counter 103 selects which of the N decoder signals will be active. The N output signals from the decoder 101 are supplied to N corresponding write enable (WEN) inputs of an N-register buffer 105. A common data input (DIN) signal 107 is supplied to the inputs of each of the N registers contained in the N-register buffer 105. If the DIN signal 107 is only 1-bit wide, then the asynchronous buffer 100 is said to be a serial buffer. If the DIN signal 107 is more than 1-bit wide, then each of the N registers in the N-register buffer 105 is similarly configured, and the asynchronous buffer 100 is said to be a parallel buffer.
When a WCLK signal 109 is asserted, the value of the DIN signal 107 will be stored into that one of the N registers that has its corresponding WEN line simultaneously asserted. The WCLK signal 109 is also supplied to an input of the write counter 103 in order to modify the WADR signal 119 (e.g., by incrementing) in preparation for the next write operation. Writing to the asynchronous buffer 100 continues in this manner, under the control of a first system (not shown).
At the same time, a second system (not shown) controls the retrieval of the data stored in the asynchronous buffer 100. A read operation occurs with every assertion of a RCLK signal 111. (Hardware for latching the data out (DOUT) signal 113 with each assertion of the RCLK signal 111 is presumed to be part of the second system, and is not illustrated in FIG. 1.) Generation of the DOUT signal 113 is accomplished as follows. Outputs from each of the N registers contained in the N-register buffer 105 are supplied to corresponding inputs of an N:1 multiplexor (MUX) 115. Selection of one of the inputs for use as the DOUT signal 113 is controlled by an m-bit wide read address (RADR) signal 121 that is supplied by a read counter 117. The RCLK signal 111 that is used by the second system for latching the DOUT signal 113 is also supplied to an input of the read counter 117 in order to modify the RADR signal 121 (e.g., by incrementing) in preparation for the next read operation. The cycle of RADR values must be the same as the cycle of WADR values in order ensure that all DIN values supplied to the asynchronous buffer 100 are also retrieved. Reading from the asynchronous buffer 100 continues in this manner under the control of the second system (not shown).
In the exemplary conventional asynchronous buffer 100, both the write counter 103 and the read counter 117 perform modulo 2.sup.m increments (or alternatively decrements) of the respective WADR and RADR signals 119, 121. Consequently, each of these address values will "wrap around" to an initial address after generating all 2.sup.m different address values. This makes it necessary to perform read operations with the same average frequency as write operations in order to prevent data stored in the N-register buffer 105 from being overwritten by newer data before it has been retrieved by the second system. That is, the respective values in the write counter 103 and the read counter 117 must never pass each other, in order to avoid a slip in the data flow (i.e., the occurrence of a data value, stored in the buffer 105, being read twice or not at all). A phase locked loop (PLL) or a "stuffing" procedure may be implemented to prevent these problems from occurring. Detailed explanations of these well-known techniques are beyond the scope of this description, however, since they do not assist an understanding of the invention.
In systems that utilize an asynchronous buffer, such as the one illustrated in FIG. 1, it is often a requirement that the buffer have a self-diagnostic capability, meaning that the buffer itself contains hardware that detects the occurrence of a hardware fault. This added function requires correspondingly additional hardware. One problem with providing this self-diagnostic capability arises from the fact that if the additional hardware is too complex, then the likelihood that the additional hardware is the source of a hardware fault increases.